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Re:Verilog Is Weird by bsder on Wednesday March 23, 2022 @04:02PM (#30782647)
And yet, for all the pissing and moaning about HDLs from software guys, I can't express a state machine in any current mainstream computer language.

For example, the current big advance in "modern" languages is "async". Which "just" instantiates an implicit state machine that you can't control.

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