The 65816 address space was segmented, like the 8086's.

Nope, the 65816 address space is flat. If you read the docs and look at the opcodes I see how it can give the impression of being segmented (with all the "bank" terminology), but it's a full 24-bit address space with no restrictions.

Sort of, at least. IIRC, program code could not execute across bank boundaries, although you could do long jumps to any 24-bit address.

Which is probably the case also for this hack. It's probably possible to devise logic that would remove this limitation, but I assume that would be mentioned in the article.

Read the article, he's thought of that. There is a trick with two registers in there that allows you to pivot from one bank to another.

More explanation in the appendix on the instruction set. The opcodes are 13, 23, eb and fb:

http://www.laughtonelectronics.com/arcana/BrideOfSon%20KK%20...

Bottom of the list.

It allows you to jump between banks, but not to overflow from one bank to another without explicit jump on the boundary.

You can always check if all address lines transitioned from 1 to 0 on an instruction fetch and increment whatever you use for PBR...

It's conceptually simple, but there are two problems:

1) you have to detect near jumps that jump back inside one bank. (at least from instruction ending on 0xffff to instruction starting on 0x0000, on the other hand you can plausibly ignore this as it is very unlikely case)

2) more importantly, I understand that this coprocessor contraption does not interact in any way with lower 16 bits of address bus. You would need to actually snoop on address bus and detect the wraparound and as this thing is built from MSI logic, detecting transition 1 -> 0 on all bits of address bus - while conceptually trivial - would require significant amount of hardware. You can detect 1 -> 0 transition only on 15th bit of address, but then you really need to detect jumps in microcode and disable this logic in case of jump.