Re:Comparing DDR5 Memory from Micron, Samsung, SK Hynix
by temac on Tuesday February 15, 2022 @06:33PM
(#30354432)
The on-die ECC for DDR5 is typically:
* mandatory (an hypothetical DDR5 without could have error rates so high it would basically not work)
* an implementation detail (if the raw error rate was not that high, there would be no on-die ECC)
* not reported to the CPU
It's a complete different beast than real ECC. It's not that it is bad or concerning, it is that it does not provide RAS services and, like ECC-less DDR4, should be reserved for consumer electronics for basically only tasks like entertainment. Actually, in a better world most consumer electronic should have real ECC (instead of none at all or implementation detail on-die) -- but sadly for now vendors do not do that.
* mandatory (an hypothetical DDR5 without could have error rates so high it would basically not work)
* an implementation detail (if the raw error rate was not that high, there would be no on-die ECC)
* not reported to the CPU
It's a complete different beast than real ECC. It's not that it is bad or concerning, it is that it does not provide RAS services and, like ECC-less DDR4, should be reserved for consumer electronics for basically only tasks like entertainment. Actually, in a better world most consumer electronic should have real ECC (instead of none at all or implementation detail on-die) -- but sadly for now vendors do not do that.