Blacksmith – Rowhammer bit flips on all DRAM devices today despite mitigations

Re:Blacksmith – Rowhammer bit flips on all DRAM devices toda... by Dylan16807 on Tuesday November 16, 2021 @02:20PM (#29245185)

> All the "classical" ECC just uses additional data lines

I know that. But DDR5, at least under normal use, increases the number of bits sent across each data line in a single memory access. So now you have 16 spare bits across the entire thing, instead of just 8. This means that even if you had 32->40 ECC before, the value you could extract from the extra bits goes up a lot with DDR5.

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Re:Blacksmith – Rowhammer bit flips on all DRAM devices toda... by eqvinox on Wednesday November 17, 2021 @12:26PM (#29255962)

Oh, sorry, I misunderstood. I don't think any implementation does that, since it would require holding back the entire burst in a buffer in the DDR controller. Which would significantly impact performance through the added latency.

But honestly I don't know — and also this seems like if some vendor wanted to take (or not take) the performance hit for extra safety, they could well deviate from everyone else.

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Re:Blacksmith – Rowhammer bit flips on all DRAM devices toda... by Dylan16807 on Wednesday November 17, 2021 @06:04PM (#29260016)

To be 100% safe, it would add latency to part of the reads. Though not much compared to the normal speed of a memory access.

To be 99% safe you could send a signal a couple nanoseconds late that says "wait, this data is bad, you should abort".

It also might make writes a bit more awkward.

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