Re:Apple’s new M1 Pro and M1 Max processors
by chasil on Monday October 18, 2021 @08:35PM
(#28913619)
If its got microcode, it's not RISC.
Re:Apple’s new M1 Pro and M1 Max processors
by dragontamer on Monday October 18, 2021 @08:41PM
(#28913654)
POWER9, RISC-V, and ARM all have microcoded instructions. In particular, division, which is very complicated.
As all CPUs have decided that hardware-accelerated division is a good idea (and in particular: microcoded, single-instruction division makes more sense than spending a bunch of L1 cache on a series of instructions that everyone knows is "just division" and/or "modulo"), microcode just makes sense.
The "/" and "%" operators are just expected on any general purpose CPU these days.
30 years ago, RISC processors didn't implement divide or modulo. Today, all processors, even the "RISC" ones, implement it.
Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ??
https://www.ibm.com/support/pages/checking-aix-protection-ag...