Apple’s new M1 Pro and M1 Max processors

Re:Apple’s new M1 Pro and M1 Max processors by chasil on Monday October 18, 2021 @08:05PM (#28913429)

Here is one meaning:

Intel microcode updates added new machine opcodes to address spectre/meltdown exploits.

On a true RISC, that's not possible.

[ Parent | on HN ]

Re:Apple’s new M1 Pro and M1 Max processors by dragontamer on Monday October 18, 2021 @08:22PM (#28913550)

https://www.zdnet.com/article/meltdown-spectre-ibm-preps-fir...

Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ??

https://www.ibm.com/support/pages/checking-aix-protection-ag...

[ Parent | on HN ]

Re:Apple’s new M1 Pro and M1 Max processors by chasil on Monday October 18, 2021 @08:35PM (#28913619)

If its got microcode, it's not RISC.

[ Parent | on HN ]

Re:Apple’s new M1 Pro and M1 Max processors by dragontamer on Monday October 18, 2021 @08:41PM (#28913654)

POWER9, RISC-V, and ARM all have microcoded instructions. In particular, division, which is very complicated.

As all CPUs have decided that hardware-accelerated division is a good idea (and in particular: microcoded, single-instruction division makes more sense than spending a bunch of L1 cache on a series of instructions that everyone knows is "just division" and/or "modulo"), microcode just makes sense.

The "/" and "%" operators are just expected on any general purpose CPU these days.

30 years ago, RISC processors didn't implement divide or modulo. Today, all processors, even the "RISC" ones, implement it.

[ Parent | on HN ]