If you are building a CMOS 2-input gate then both NAND and NOR use 4 transistors. (2 NMOS and 2 PMOS each)

The reason NAND is preferred is that NMOS transistors have roughly half the resistance of a PMOS transistor of the same size. This means that to get a gate with pull-up and pull-down networks of equal strength (which is usually desirable), the NOR gate needs very large PMOS transistors and tiny NMOS while the NAND gate has all of its' transistors equally sized and relatively small.

The result is that NAND gates are smaller in size and slightly quicker than an equivalent NOR gate.

In standard NMOS or PMOS circuitry, both a NAND gate and a NOR gate require two transistors each (and a resistor, which is usually actually a transistor as well). CMOS requires four transistors for both a NAND gate or a NOR gate. It's only in TTL logic, where you can have a single transistor with multiple emitters that a NAND gate uses fewer transistors.

It's fascinating that silicon has not completely eliminated the asymmetries that were a way of life in vacuum tube circuits.

Depends on the transistor technology you are using. It's possible to create bipolar NORs as compactly as CMOS NANDs.