You could implement your design in nmigen [1], use it to generate either verilog or rtlil, then use yosys (via [2]) to reduce it to an AND and NOT circuit (using the 'aigmap' command), then visualize it with [3]

[1]: https://github.com/nmigen/nmigen

[2]: https://yowasp.org

[3]: https://github.com/nturley/netlistsvg