You could implement your design in nmigen [1], use it to generate either verilog or rtlil, then use yosys (via [2]) to reduce it to an AND and NOT circuit (using the 'aigmap' command), then visualize it with [3]

[1]: https://github.com/nmigen/nmigen

[2]: https://yowasp.org

[3]: https://github.com/nturley/netlistsvg

I'm building a CPU out of transistors in Python. Feedback (even just to tell me what an idiot I am!) and any help is highly appreciated :)

Sounds like a fun project, many years ago I built a POV led wand that used an 8 bit parallel adder made from transistors, a 555 timer and an EEPROM. That might be a good hello world type project to tackle on your way to the CPU goal.

I like projects like this! You may want to add to support and use VCD to dump the waveform and see the circuit's data flowing through time.

https://en.m.wikipedia.org/wiki/Value_change_dump

Do you have any demos of how this library works when used in something complex? Also, do you have any ways to export the logic defined into some data structure? This would allow you to bolt on compilers to translate into a netlist or FPGA.

Now there are a bunch of words I don't understand here :D

Right now there are no demos. I only have a few loose components, not enough to build anything useful (the tests do instantiate them correctly, does it count as a demo? :D)

Regarding exporting the logic, it could be a nice idea, but I have no idea where to start. Thoughts?

Have you already checked out: https://www.myhdl.org/?