This dude explained-it so well that i was astonished as to why i didn't 'get' before.
[the first video you can skip to 1:45] <https://www.youtube.com/watch?v=7OuUiwI8fDk>
[the whole series] <https://www.youtube.com/playlist?list=PLL_nf1OmixTTd7rEoqoM6...>
There is also Dave Jones' op-amp tutorial at EEVBlog (if you like Aussie accents and a bit more detailed/technical explanation yet still targeted at beginners) <https://www.youtube.com/watch?v=7FYHt5XviKc>
1. The inputs draw no current
2. If there is negative feedback present, the output will do whatever is necessary to render the two inputs equal
So you can write the equations for the voltages at the two inputs, include an equation that sets them equal, and solve for the output. To handle circuits like filters, you have to solve using complex numbers. This will be good enough to derive the design formulas in the handbooks.
These days, a third good rule is:
3. Buy an op amp that works as well as needed to obey rules 1 and 2 in your application. Op amps have made huge strides in terms of functionality and ease of design since I was in college 4 decades ago.
It's easier to understand analog circuits without knowing the above because you are dealing with concrete components that abstract a lot of details away from you.
What drove me down this path is when one day I asked myself what is voltage? Why do they use the water pressure example to explain it? We are familiar with V = IR but that doesn't explain what voltage is just like an apple falling on the ground doesn't explain gravitational force.
Don't be surprised if this journey takes you down to quantum mechanics.
I cannot emphasize this enough for those who have a "water in a pipe" mental model of DC electric circuits but struggle to intuitively grasp AC and RF concepts like filters, fields, transformers, antennas, or even buck/boost converters. Once you're able to mentally reduce some of these circuits to an understanding of the forces upon a single electron at any point in the circuit at any point in time, you being to be able to create your own designs rather than relying on the examples of others.
When you calculate this with the feedbacks, it makes sense.
The full explanation is that the + and - terminals are a virtual short. Negative feedback will try to set the + and - terminals to the same voltage but no current flows between the two locations.
The amount of current (and the limitations of voltages) are set by the quality of the opamp. Better opamps have closer voltages at faster speeds at better currents.
Cheaper opamps will have a bit of error and diverge from the model. The delay can be largely modeled by capacitance over the + and - terminals (among other models of opamp errors)
But even a cheap opamp will keep the + and - sides within .05 Volts or so under typical circumstances.
With the infinite gain concept you can use a limit to calculate the behavior of any circuit.
This is only true for negative feedback cases but that's the most common case.
It is easier in most cases than infinite gain model IMO. Once you have voltage and current of that location figured out, everything else in the circuit is solvable by freshman level analysis.
1. If current flows through the base-emitter junction, then there is a voltage of roughly 0.6 V across that junction.
2. The collector current is roughly proportional to the base current, by the beta constant, which is about 10 for big transistors and 100 for little ones.
There are some rare textbook cases such as logarithmic amplifiers that just have to be looked up, following the Ebers-Moll equation.
As for FETs... once you get the type correct (P or N type, enhancement or depletion mode, which I still have to look up or find an example circuit), gate-source voltage is constant, gate current is zero, and the drain current equals the source current.
As for vacuum triodes... they behave much like N type JFETs.
You can check your analysis of any of these circuits using the wonderful LTSpice.
I agree that LTSpice is wonderful. It would be even more wonderful if it was open sourced.
But because it's been closed source, it has basically stagnated for the past 10 years.
But then, this whole notion of sharing your blueprints and designs with the whole world so the whole world can improve them is such a gigantic impedance mismatch with the culture of the EE crowd in general that its quite unlikely to ever happen.
I used to have this problem too. Turns out it's easier to work with than you think: the symbol actually describes things pretty well.
(This ought to be illustrated, but unfortunately I haven't got the time for that.)
JFETs are pretty easy. They're always depletion devices, so their channel always starts conducting: it's solid on the symbol. The gate is directly connected to the channel, so it touches, it's symmetrical, so we draw the gate in the center (though I will draw it near one terminal if I am trying to communicate "hey reader, this one is the source, look at it first"), and there's a "diode arrow" that has either N-type material at the channel end (N-channel part!) or P-type material at the channel end (P-channel part!).
MOSFETs are more confusing, but it still isn't bad. They're actually four-terminal devices; we'll add the body in a moment. But their defining feature is that insulated gate, so we can show that by pulling the gate away from the channel, drawing it as a solid line running parallel to the channel. The gate comes off it next to the source, to reinforce the idea that V_GS is the controlling voltage here.
The body (also called bulk or substrate, though be careful with that last one as it is not actually the substrate in all processes) is what the channel gets formed out of, so let's add the body terminal as coming out of the middle of the channel. The body diode is now formed between the channel and the body proper. We draw it relative to the channel: for N-channel parts, draw the "diode arrow" with the N-type material at the channel and the P-type material at the body terminal, or vice versa for a P-channel part.
The body gets tied off to the source in the vast, vast majority of MOSFETs (and indeed this sometimes is part of what singles out one terminal as the source), so we can do that right now by drawing a line between them. We've now made everything we need to draw the symbol of or to explain a depletion MOSFET that works rather like the JFETs previously discussed.
But most MOSFETs aren't depletion mode, they're enhancement mode. And so we indicate that by drawing the channel as a dashed line, rather than solid. Since there are three terminals, attached to the channel, D, B, and S, we draw the channel as three dashes, one for each terminal.
Now we're done. Walking through that exercise really helped me understand just what these critters are inside and why we draw them the way we do. I hope it helps someone else, too. And I especially hope it might inspire any analog designer who doesn't draw things correctly, perhaps preferring the simplified symbols created by the simplified disciplines (cough digital cough) who can ignore that such things as "linear mode" operation even exist, to draw things using the correct symbols, which are complicated because they tell a rather complicated device's story.
(Bonus factoid: ever wonder why P-channel depletion MOSFETs don't exist? As far as I've been able to put together, they do exist. It's just that when you try to manufacture them in the usual processes, the process inevitably causes you to end up with charge trapped under the gate... which turns the poor things off for you. So they're back to being enhancement mode! This effect doesn't bother N-channel parts, since it happens to try to turn them on. I believe this effect can be overcome with careful process control, but no one thinks it would be profitable to bring discrete devices into mass manufacturing. A few integrated parts with P-channel depletion FETs inside have shipped in full volume for decades.)
These rules are non-intuitive if you are thinking raw circuits but are very easy to use if you hold your nose and just take the model on faith (because the model pretty much works all the time).
Only if you design the innards of an Op Amp does the model become less shiny and reality creeps in.
So when you design with an op amp you use certain "simplifying magical assumptions:
1. There is zero input leakage so you can KCL both input and feedback current pretending that the op amp isn't affecting either of these. That's pretty much a valid assumption until you design ultra low current circuits with an op amp. But then you'll likely want to switch to an "instrumentation op amp" of a specific design for such applications. That's <<1% of anyone.
2. The input voltages (+ and -) "magically" can be assumed to always be equal without any external current or voltage seeming to cause it to happen. This is due to the innards of the op amp design plus feedback.
These two assumptions mean that you can apply simply circuit analysis and you quickly attain accurate predictions of how the circuit will work (gain, bandwidth, etc.). Even most EEs work with this. Only analog IC designers go beyond this.