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A comment on The Ice-V: a simple, compact RISC-V RV32I implementation in Silice. Parent comment

Re:The Ice-V: a simple, compact RISC-V RV32I implementation ... by brucehoult on Monday June 21, 2021 @08:56PM (#27586694)
And for FPGA stuff intersecting with RISC-V:

@jangray @BrunoLevy01 @OlofKindgren @mithro @iamtommythorn @YosysHQ @oe1cxw @wavedrom @bunniestudios

There is plenty of quality content on Twitter, and it's easy to avoid the drama llamas.

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