The Ice-V: a simple, compact RISC-V RV32I implementation in Silice

Re:The Ice-V: a simple, compact RISC-V RV32I implementation ... by mastax on Sunday June 20, 2021 @11:34PM (#27576055)

You have to find and follow people you want to see - and ignore all the "New and Trending" that Twitter tries to shove on you.

I don't use Twitter often, but it seems like the social media of choice for semi-public techy millenials so I follow a bunch of that type. Every time I go on twitter (~monthly) I have a good time seeing all the fun projects that have been happening and all the cross-pollination between different interesting people.

A starting point:

@kenshirriff @whitequark @BenKrasnow @foone @ID_AA_Carmack @MarcoReps @craig_jbishop @jonhoo @TheSignalPath

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Re:The Ice-V: a simple, compact RISC-V RV32I implementation ... by brucehoult on Monday June 21, 2021 @08:56PM (#27586694)

And for FPGA stuff intersecting with RISC-V:

@jangray @BrunoLevy01 @OlofKindgren @mithro @iamtommythorn @YosysHQ @oe1cxw @wavedrom @bunniestudios

There is plenty of quality content on Twitter, and it's easy to avoid the drama llamas.

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Re:The Ice-V: a simple, compact RISC-V RV32I implementation ... by sydthrowaway on Sunday June 20, 2021 @11:41PM (#27576087)

Thanks.

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