Re:Apple’s M1 Positioning Mocks the Entire x86 Business Model
by userbinator on Friday April 23, 2021 @03:50PM
(#26918478)
Leakage is actually a significant part of idle power consumption, especially at smaller process sizes, so much that some CPUs have the ability to turn off parts of caches when idle.
I repeat my stance that x86 instruction decoding is a tiny part of a processor, and things like vector units (which are also often powered down when idle) and reordering logic take far more power.
There's a paper about this that compares the efficiency of different ISAs, and basically concludes that ARM and x86 are no different in that respect. Only MIPS is an awful outlier.
https://www.extremetech.com/extreme/188396-the-final-isa-sho...
Re:Apple’s M1 Positioning Mocks the Entire x86 Business Model
by adwn on Saturday April 24, 2021 @01:25AM
(#26922483)
That paper doesn't show what you think it shows. There are too many variables between these CPU implementations to support the conclusion that the ISA doesn't matter for power consumption.
[1] Well, mostly. There is such a thing as static power draw, but I suspect that the transistors in the L3 cache are optimized to have lower static leakage than the transistors in the core logic, which are optimized to be fast.