Those headlines are correct, and were at the time this article was written as well. Intel's first 10nm process was completely broken, and their current less-dense 10nm process is still barely usable. Any density advantages Intel was planning on their 10nm having over TSMC 7nm are meaningless at this point. Higher density is pointless unless you can get yields that are good enough to ship chips that are meaningfully better on power, performance and price.

Please note that Dennard's scaling has long subsided, gate length reductions do not automatically comes with gains for every metric anymore, notably leakage current. Previous nodes are more power-efficient for some uses, like infrared remotes.

The criticism is that feature size isn't useful for chip designers to choose a fab anymore, so they should be ignoring it too nowadays. (The meta criticism is that they already know it, no need to point it out.)

In plain english, when someone conveys made up information for their gain, we call this lying