HBM3 wasn't just supposed to be about speed. It also offers a 512-bit option that doesn't require a silicon interposer. I'd guess this was added to make cheaper consumer GPU designs possible.

I suspect they're using the HBM2 spec for the narrow bus and cheaper interposer while keeping speeds lower and only using a couple stacks instead of the 16 or so HBM2 stacks required for those 2Tb/s speeds you mention. It makes sense given that their chip likely couldn't use a huge amount of bandwidth anyway.