SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by volta83 on Friday April 16, 2021 @11:23AM (#26834987)

HBM2 is like 2Tb/s, how is HBM3 7GB/s ?

[ Parent | on HN ]

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by vmception on Friday April 16, 2021 @05:20PM (#26839202)

HBM3 was expected to be like 4GB/s per pin which was seen as double HBM2 per pin, so this is therefore almost even double that, which is good news

The HBM2 total memory bandwidth is like 2TB/s, just different scale

Anyway I could totally be using wrong nomenclature and terminology, feel free to discuss, these aren't assertions or aren’t strongly held assertions

[ Parent | on HN ]

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by hajile on Friday April 16, 2021 @12:48PM (#26836228)

HBM3 wasn't just supposed to be about speed. It also offers a 512-bit option that doesn't require a silicon interposer. I'd guess this was added to make cheaper consumer GPU designs possible.

I suspect they're using the HBM2 spec for the narrow bus and cheaper interposer while keeping speeds lower and only using a couple stacks instead of the 16 or so HBM2 stacks required for those 2Tb/s speeds you mention. It makes sense given that their chip likely couldn't use a huge amount of bandwidth anyway.

[ Parent | on HN ]

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by virtuallynathan on Friday April 16, 2021 @11:26AM (#26835031)

I think that’s per-Pin bandwidth?

[ Parent | on HN ]