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Re:Xilinx Opens Up Vitis HLS Tool for FPGAs by ancharm on Wednesday March 10, 2021 @08:00PM (#26418780)
Higher level hardware design languages that better interop with software are desperately needed, but I don't know if C/C++ is the right UI/abstraction.
Re:Xilinx Opens Up Vitis HLS Tool for FPGAs by hctaw on Thursday March 11, 2021 @12:54AM (#26420743)
Look at Chisel. I agree that C/C++ is the wrong abstraction but that's because using a HDL is more like meta programming in a declarative markup language that needs to be embedded in a higher level language for automation and verification than to compile imperative operations into silicon.
Re:Xilinx Opens Up Vitis HLS Tool for FPGAs by UncleOxidant on Wednesday March 10, 2021 @09:18PM (#26419393)
I don't think so either. One thing that's interesting here is that this ties into LLVM - perhaps other LLVM languages like Julia or Rust could interop?
Re:Xilinx Opens Up Vitis HLS Tool for FPGAs by ancharm on Wednesday March 10, 2021 @09:29PM (#26419474)
I've kind of always felt that synthesizable Verilog/SystemVerilog was good, but the verification side was just too complex and had too much bloat. Testing hardware with Python (like Cocotb) feels more on the right track as a high level UI.

But easily pluggable APIs for foreign SW languages are key as well. Hardware software co-design is only becoming more important.