MIPS Becomes RISC-V

Re:MIPS Becomes RISC-V by zdw on Monday March 08, 2021 @03:52PM (#26391362)

SPARC is well known to be different enough (big endian, register windowing of the stack, alignment, etc.) that it exposes a lot of bugs in code that would be missed in a little-endian, x86 derived monoculture.

https://marc.info/?l=openbsd-bugs&m=152356589400654&w=2

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Re:MIPS Becomes RISC-V by simias on Monday March 08, 2021 @04:18PM (#26391712)

I always found SPARC's stack handling to be very elegant and I write enough of low level code that these architectural details do from time to time impact me, but isn't it largely irrelevant for the industry at large?

After all MIPS's original insight was that machine code was now overwhelmingly written by compilers and not handwritten assembly, so they made an ISA for compilers. I think history proved them absolutely right, actually these days there are often a couple of layers between the code people write and the instructions fed into the CPU.

I guess my point is that nowadays I'm sure that many competent devs don't know what little-endian means and probably wouldn't have any idea of what "register windowing of the stack" is, and they're completely unaffected by these minute low level details.

Making it a bit easier for OpenBSD to find subtle bugs is certainly nice, but that seems like a rather weak argument for the vast amount of work required to support a distinct ISA in a kernel.

Honestly I'm not convinced by the argument for diversity here, as long as the ISA of choice is open source and not patent encumbered or anything like that. Preventing an x86 or ARM monoculture is worth it because you don't want to put all your eggs in Intel or Nvidia's basket, but if anybody is free to do whatever with the ISA I don't really see how that really prevents innovation. It's just a shared framework people can work with.

Who knows, maybe somebody will make a fork of RISC-V with register windows!

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Re:MIPS Becomes RISC-V by goatinaboat on Tuesday March 09, 2021 @03:45AM (#26396692)

I'm sure that many competent devs don't know what little-endian means and probably wouldn't have any idea of what "register windowing of the stack"

These days "bare metal programming" means writing raw HTML yourself in a text editor, no CSS, no JS.

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Re:MIPS Becomes RISC-V by tyingq on Monday March 08, 2021 @05:37PM (#26392605)

I had a neat experience a long time ago when I wrote a Perl XS module in C, in my x86 monoculture mindset. When you deploy something to their package manager (CPAN), it's automatically tested on a lot of different platforms via a loose network of people that volunteer their equipment to test stuff...https://cpantesters.org.

So, I immediately saw it had issues on a variety of different platforms, including an endianess problem. Cpantesters.org lets you drill down and see what went wrong in pretty good detail, so I was able to fix the problems pretty quickly.

It used to have a ton of different platforms like HPUX/PA-RISC, Sun/Sparc, IRIX/MIPS and so on, but the diversity is down pretty far now. Still lots of OS's, but few different CPUs.

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