MIPS Becomes RISC-V

Re:MIPS Becomes RISC-V by dralley on Monday March 08, 2021 @02:55PM (#26390684)

I'm curious if someone could explain the architectural differences between ppc64le and aarch64? I've always heard they are quite similar.

[ Parent | on HN ]

Re:MIPS Becomes RISC-V by arnd on Monday March 08, 2021 @07:56PM (#26393867)

MIPSr6, aarch64 and riscv are siblings born from MIPSr5 plus the best of other RISC architectures.

ppc64le and 32-bit Arm are part of the wider family, but have some notable differences that make them slightly less RISC-like. Both include e.g. more complex condition code handling and instructions that operate on more than three registers.

[ Parent | on HN ]

Re:MIPS Becomes RISC-V by tyingq on Monday March 08, 2021 @03:05PM (#26390776)

Since you mentioned ppc64le, there's also aarch64eb (arm64 in big endian mode). I saw that NetBSD supports it. It seems like support for other operating systems is limited mostly because of issues around booting...not the actual kernel or userland itself.

[ Parent | on HN ]