MIPS Becomes RISC-V

Re:MIPS Becomes RISC-V by ChuckMcM on Monday March 08, 2021 @02:39PM (#26390483)

It was unclear if "v8" of the MIPS architecture is a re-branded RISC-V or if v8 MIPS is a combined RISC-V + MIPS or what.

[ Parent | on HN ]

Re:MIPS Becomes RISC-V by esturk on Monday March 08, 2021 @06:38PM (#26393180)

"In this context, the “8th generation” refers to seven generations of the traditional MIPS architecture, followed by an upcoming RISC-V design. It sounds like the company is implying that this is a smooth transition with some level of compatibility between the old and the new. It isn’t. It’s a clean break as the company switches from the old CPU design, that it owned, to a new one that’s in the public domain."

[ Parent | on HN ]

Re:MIPS Becomes RISC-V by arnd on Monday March 08, 2021 @07:20PM (#26393564)

Mips R6 (Warrior m62xx/i6400/i6500/p6600) was already somewhat incompatible with R5 and earlier, the seventh generation nanomips i7200 was incompatible with that again.

[ Parent | on HN ]