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A comment on MIPS Becomes RISC-V. Parent comment

Re:MIPS Becomes RISC-V by arnd on Monday March 08, 2021 @07:20PM (#26393564)
Mips R6 (Warrior m62xx/i6400/i6500/p6600) was already somewhat incompatible with R5 and earlier, the seventh generation nanomips i7200 was incompatible with that again.
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