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A comment on Lion: A formally verified, 5-stage pipeline RISC-V core. Parent comment

Re:Lion: A formally verified, 5-stage pipeline RISC-V core by GregarianChild on Thursday March 04, 2021 @10:17AM (#26343436)
There is a lot of resistance to dropping Verilog among working processor designers in my experience. Interestingly, LLHD is being folded into CIRCT [1] which is part of LLVM.

[1] https://github.com/circt

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Re:Lion: A formally verified, 5-stage pipeline RISC-V core by sitkack on Friday March 05, 2021 @08:17AM (#26356500)
I am trying to come to grips with this, this looks like this sets up the condition where the whole language compiler stack can change the target architecture and implementation.

This feels like some powerful algebraic property has been satisfied.

https://en.wikipedia.org/wiki/Popek_and_Goldberg_virtualizat...

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