Re:In the future even your RAM will have firmware; and the s...
by PhantomGremlin on Thursday February 04, 2021 @08:43PM
(#26032087)
latency is too important
Yeah, you would think so. But it really hasn't improved all that much over the years. (Of course, that's partially because it's hard to do!).
Roughly speaking, when I designed with DRAM in 1983, the access time from RAS was 150 ns for the most popular parts. Now, with DDR4, you're talking CAS latency of about 10 ns, an improvement of 15x.
In the same timeframe CPU clock rate increased from about 10 MHz to about 3000 MHz, an improvement of 300x.
I grok your comment about perhaps having two levels of DRAM, but the whole memory hierarchy thing is already crazy. Most computers already have 3 levels of cache ahead of the DRAM.
Re:In the future even your RAM will have firmware; and the s...
by datameta on Thursday February 04, 2021 @09:35PM
(#26032403)
With Storage Class Memory aka Persistent memory becoming a talked about thing in the industry they're not too far off base. It sits right between capacitive memory and nand flash; may end up being the DRAM's page file and the SSD's cache.
Re:In the future even your RAM will have firmware; and the s...
by justaguy88 on Thursday February 04, 2021 @09:05PM
(#26032229)
Latency is very important, but cost is even more important.
If there was cheaper lower latency DRAM they'd use it
Re:In the future even your RAM will have firmware; and the s...
by sitkack on Thursday February 04, 2021 @08:42PM
(#26032078)
Main memory will move to an HBM, "regular" ram beyond the first 32,64 ... GB will be DDRX, then it will be pmem (Optane, etc). We will just keep getting more layers in the hierarchy.
Re:In the future even your RAM will have firmware; and the s...
by wahern on Thursday February 04, 2021 @10:22PM
(#26032703)
Yep. Because memory access fundamentally scales in O(sqrt(N)) time, not O(1). http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html
Re:In the future even your RAM will have firmware; and the s...
by ardy42 on Thursday February 04, 2021 @09:23PM
(#26032333)
> Everything old is new again. They tried this with FB-DIMMs in the early 2000s and it didn't go well:
IIRC, Rambus RDRAM was also serial, or at least less parallel than conventional DRAM.
https://en.wikipedia.org/wiki/Fully_Buffered_DIMM
That SERDES chip unavoidably increases latency, roughly doubling it. This isn't likely to catch on as the only kind of DRAM in the system; latency is too important.
Maybe we'll see successful systems with two levels of DRAM: small low-latency parallel DRAM and a large heap of higher-latency serial DRAMs. That's plausible.