Re:The brain's 5-million core, 9 Hz computer
by Brashman on Sunday May 29, 2011 @07:39PM
(#2597927)
Harder is not necessarily true. It depends on what you're trying to build.
In terms of QDI Async circuits, the main disadvantage is an increase in wires. In synchronous circuits, a slow enough clock ensures that the computation is completed (propagates through transistors) before moving on to the next clock cycle. For QDI async, the replacement is to have a handshaking protocol to ensure correctness as values pass through the transistors/computation. The handshaking increases the number of wires needed (and thus silicon area).
In terms of QDI Async circuits, the main disadvantage is an increase in wires. In synchronous circuits, a slow enough clock ensures that the computation is completed (propagates through transistors) before moving on to the next clock cycle. For QDI async, the replacement is to have a handshaking protocol to ensure correctness as values pass through the transistors/computation. The handshaking increases the number of wires needed (and thus silicon area).