Re:New Transistor Structures At 3nm/2nm
by ashz8888 on Monday January 25, 2021 @05:39PM
(#25909934)
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture.
See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
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Re:New Transistor Structures At 3nm/2nm
by colejohnson66 on Monday January 25, 2021 @09:56PM
(#25911879)
Why is that? What’s the point in calling it “3nm” when it’s not?
<rant>
Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies. Just because everyone does it doesn’t make it right.
</rant>
Re:New Transistor Structures At 3nm/2nm
by souprock on Tuesday January 26, 2021 @03:59AM
(#25913799)
Clearly we need a better measurement. I suggest picking an open core, then reporting the number that can be produced per square meter. Some choices:
https://en.wikipedia.org/wiki/Category:Open_microprocessors
The IBM A2 and the UltraSPARC T2 look like sane choices. Perhaps there is a suitable RISC-V.
So then comparing processes, we could say that process X can do 54255 chips per square meter and process Y can do 83802 chips per square meter.
There is such standard measure but it is the number of transistors for a square millimeter[1].
[1] https://en.wikipedia.org/wiki/Transistor_count#Transistor_de...
Re:New Transistor Structures At 3nm/2nm
by souprock on Tuesday January 26, 2021 @06:45PM
(#25922417)
That is not a great measurement. Transistors can be of different types, each with different value in terms of making products work. Other things matter too: metal, pads, die separation saw cuts, e-fuses, diodes, resistors, and capacitors. Nobody cares about transistors that can't be hooked up to anything.
Re:New Transistor Structures At 3nm/2nm
by ashz8888 on Tuesday January 26, 2021 @04:45AM
(#25914036)
Well because of tradition. Historically it made sense to define new technology node in terms physical gate length. But now even if that's not viable, they continue to do so for better marketing I guess.
Re:New Transistor Structures At 3nm/2nm
by colejohnson66 on Tuesday January 26, 2021 @08:57AM
(#25915779)
But if we’re not basing it on reality, when does “5nm” become “3nm”? And the fact that it’s just marketing makes comparing across manufacturers (eg. Intel vs. TSMC) impossible.
Re:New Transistor Structures At 3nm/2nm
by ericlewis on Monday January 25, 2021 @07:59PM
(#25911120)
Why is that? (Sorry, the paper is beyond my understanding)
Re:New Transistor Structures At 3nm/2nm
by ashz8888 on Tuesday January 26, 2021 @04:42AM
(#25914018)
Short answer is tradition. Historically they were able to stay on Moore's law with each new technology node representing the physical gate length. Currently however, even if they can't continue on that trajectory they still define the next technology node that way.