Probably not.

iCE40 FPGAs come with up to 7,680 logic cells.

The J1 was designed for a board with a Xilinx XC3S1000, which has 17,280 logic cells.

There are RISC-V cores that fit in about 1k luts. One could build a NoC of RISC-V using an XCS1000.

This is probably because the RAM is internal to the FPGA:

> A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA.

I'd guess the CPU itself would easily fit into an iCE40 (given that RISC-Vs are fitting and the J1 should be simpler) with the RAM external. Several of the iCE40 boards have external RAMs

Even the iCE UP5K has a whopping internal 1Mb RAM.