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Re:BeagleV – An affordable RISC-V computer designed to run L... by brucehoult on Wednesday January 13, 2021 @10:39AM (#25763308)
If you're doing something embedded nothing prevents you implementing multiply but not divide. RISC-V gcc has an option to use an instruction for multiply but runtime library call for divide.

In fact, even if you claim to implement the M extension (both multiply and divide) all that is necessary is that programs using those opcode work -- but that can be via trap and emulate. If your overall system can run binaries with multiply and divide instructions in them then you can claim M-extension. Whether the performance is adequate is between you and your customers. Note that there are also vast differences in performance between different hardware implementations of multiply and divide, with 32-64 cycle latencies not unheard of.

The same applies for implementing a subset of other extensions in hardware. You can implement the uncommon ones in the trap handler if that will meet your customer's performance needs.

Re:BeagleV – An affordable RISC-V computer designed to run L... by IshKebab on Wednesday January 13, 2021 @02:52PM (#25767119)
Yeah if you're willing to do something completely non-standard of course you can do whatever you want.

> Note that there are also vast differences in performance between different hardware implementations of multiply and divide, with 32-64 cycle latencies not unheard of.

Yes that is exactly the problem.

Re:BeagleV – An affordable RISC-V computer designed to run L... by brucehoult on Thursday January 14, 2021 @06:57PM (#25784890)
This problem exists even among different CPUs that all implement the M extension in hardware -- or different CPUs in ISAs where multiply and divide are not optional, such as x86 or aarch64.

The worst (but conforming) hardware implementations are barely better than the best software emulations -- and maybe worse if the software emulation is running on a wide OoO CPU.