Memory access on the Apple M1 processor

Re:Memory access on the Apple M1 processor by astrange on Wednesday January 06, 2021 @09:14PM (#25666427)

There are real differences in processors caused by their ISAs - it's not true that decoders mean it's all the same RISC in the backend.

For instance, it's hard to combine instructions together, which is actually an advantage for x86 (the complex memory operands come for free). But it also guarantees memory ordering that ARM doesn't which is a drawback.

I'm not sure how important this is in practice.

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Re:Memory access on the Apple M1 processor by nkurz on Wednesday January 06, 2021 @09:27PM (#25666540)

> For instance, it's hard to combine instructions together, which is actually an advantage for x86 (the complex memory operands come for free).

True, although I just looked at the ARM assembly for Daniel's example, and it's making good use of "ldpsw" to load two registers from consecutive memory with a single instruction. So in this particular case, it may be a wash.

> But it also guarantees memory ordering that ARM doesn't which is a drawback.

Yes, I wasn't considering the memory model to be part of the instruction set. I agree that in general this could be a big difference in performance, although I don't think it comes up in Daniel's example.

I added a comment to Daniel's blog with my guess as to what's happening to cause the observed timings in his example. Feedback from anyone with better knowledge of M1 would be appreciated.

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