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Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by webmobdev on Sunday January 03, 2021 @06:58PM (#25626498)
Theoretically, Now you can create "micro-codes" in the CPU for your specific needs - e.g. scientists do a lot of calulation and would like a processor optimised for that. Now they can use the FPGA to do it. You want a CPU instruction that is optimised for something else - you can program the FPGA for that.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by asimpletune on Sunday January 03, 2021 @07:34PM (#25626718)
Or maybe a compiler could recognize that optimization is possible and create it for you
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by Kuinox on Sunday January 03, 2021 @08:48PM (#25627154)
More likely a JIT can do that.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by LeifCarrotson on Sunday January 03, 2021 @09:04PM (#25627232)
The FPGA can't be reprogrammed fast enough for the JIT approach to work, unless you're running computations that take many minutes or hours. I suppose that does apply to some workloads, but it would be tough to ask your JIT to solve the halting problem and guess whether a workload will last 10 seconds or take longer than that.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by penteract on Sunday January 03, 2021 @09:13PM (#25627277)
For a JIT, the easy way to guess is to wait until it's already taken 10 seconds and if it hasn't stopped, assume it will take at least 10 more.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by Kuinox on Monday January 04, 2021 @06:01AM (#25629784)
I would say that program that are run and exit immediatly are a minority of what is produced with languages. A lot of web server, services, gui are produced in JIT languages and have a timespan of multiple minutes. AFAIK FPGA reprogrammation time depends on the size of your edit, and your hardware, the article says that they expect to reprogramm it on a program load, so I don't think it will be that slow.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by bcrosby95 on Monday January 04, 2021 @01:21AM (#25628359)
Why can't a JIT program the FPGA based upon previous runs through the same set of code? IIRC the JVM won't rest on its final optimizations until it runs a chunk of code hundreds (or thousands? I forget) of times.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by pjmlp on Monday January 04, 2021 @01:40AM (#25628436)
Depends pretty much on which JVM we are talking about, Java is like C, plenty to chose from.

In what concerns OpenJDK that is configurable via the -XX flags.

Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by snicker7 on Monday January 04, 2021 @01:26AM (#25628379)
In scientific computing, that is the typical workload. That is why, say, Julia exists despite having a ridiculous JIT overhead.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by chippiewill on Monday January 04, 2021 @01:07PM (#25635379)
Isn't that a general warm-up problem with JITs though?
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by pjmlp on Tuesday January 05, 2021 @04:02AM (#25643594)
With any kind of compilation process, a balancing act between time spend waiting and the quality of generated machine code.
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by robomartin on Monday January 04, 2021 @07:56PM (#25640545)
I've been doing that for years. I have created custom microcoded CPU's in FPGA's for tasks where it would provide an advantage. One example I remember was a microcoded real time image warping engine.