Firstly, (for the uninitiated) Bluspec is both a Haskell DSL (Bluespec Classic) and a Verilog-like language (Bluespec SystemVerilog)

It compiles to Verilog, but the stack is much more integrated than other similar compile-to-verilog HDLs - the simulator is similar to verilator and much easier to get started with.

I'm kind of beginning to feel that Haskell isn't a good medium for HDL code - Verilog already encourages unreadable names like "mem_chk_sig_state" and Haskell code is almost unstructured to my eye (I like functional programming but it seems hard to keep it readable because of the style it imposes - the flow is there but the names are usually way too short for my taste)

I'm pretty sure Bluespec and SpinalHDL compile to Verilog. Chisel uses it's own IR (FIRRTL). I think Migen used to target Verilog, but now targets (one of?) the IR(s) that Yosys supports (RTLIL?).