It may be interesting to look at a more completely labeled die image (eg. a recent AMD laptop chip [1]).

I/O controllers, various PHYs, the display pipeline and the media engine account for a significant fraction of chip.

We also know the M1 has an integrated SSD controller, ISP and Thunderbolt which probably take a good chunk of room too.

[1] https://potatopc.net/amd-renoir-die-annotation-raises-hopes-...

> We also know the M1 has an integrated SSD controller, ISP and Thunderbolt which probably take a good chunk of room too.

SSD controller and even Thunderbolt. That's the most integrated SoC I've heard of.

Cache, GPU, Secure Enclave, Neural processors, peripheral controllers. GPU takes the lion’s share.

The Cache, GPU, and NPU are all already labeled in the image.

The Secure Enclave is a good one to point out that is in the unlabeled space.

Certainly some non-DDR peripherals are in the unlabeled space, but it would be neat to have a more comprehensively labeled diagram. I wouldn't expect most peripherals to take up so many transistors compared to the processor cores.

There's probably 4 lanes of pcie to connect the nvme ssd to, a couple more lanes to run the thunderbolt controllers, 2-3 usb controllers + a hub to connect the keyboard and touchpad, an audio dac and some thermal and power usage monitoring. They might even put the ethernet controller that shoes up on the Mac mini in there.

Sorry, was looking at the marketing image. The enclave would be quite tiny though. Id say most of the undocumented part is custom glue logic which isn’t particularly identifiable.