Re:The CPUs of Spacecraft Computers in Space
by yholio on Saturday December 19, 2020 @04:27AM
(#25476304)
I have absolutely no idea why someone would connect the upper bits of the CPU address bus to the lower bits of the memory, if this is what the GP refers to. Their naming scheme seems irrelevant.
Almost all modern memory is built in a large matrix where the upper bits select the row into a buffer and the lower bits control a multiplexer that selects a slice of that row. Scanning incrementally through the memory will hit the fast multiplexer path and result in much faster access.
Propagating into the whole matrix at each increment is not only a power draw but a massive slowdown.
Almost all modern memory is built in a large matrix where the upper bits select the row into a buffer and the lower bits control a multiplexer that selects a slice of that row. Scanning incrementally through the memory will hit the fast multiplexer path and result in much faster access.
Propagating into the whole matrix at each increment is not only a power draw but a massive slowdown.