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A comment on ARM and Lock-Free Programming. Parent comment

Re:ARM and Lock-Free Programming by my123 on Tuesday December 01, 2020 @06:02AM (#25264191)
A weak memory model. See https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RIS... (by Dan Lustig at Nvidia, NV is both very involved in Arm and RISC-V).
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Re:ARM and Lock-Free Programming by zozbot234 on Tuesday December 01, 2020 @08:17AM (#25264839)
It has a weak memory model by default, but you can opt in to TSO (like x86) as an optional extension.
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Re:ARM and Lock-Free Programming by my123 on Tuesday December 01, 2020 @08:19AM (#25264848)
And for Arm too, you can ship stronger memory models up to SC.

There's also the RCpc extension for memory accesses w/ another memory model there.

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Re:ARM and Lock-Free Programming by jabl on Tuesday December 01, 2020 @01:05PM (#25267841)
Is RCpc still multi-copy atomic? (Which AFAIK is a guaranteed behavior of the Aarch64 memory model)
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Re:ARM and Lock-Free Programming by my123 on Wednesday December 02, 2020 @01:59PM (#25279982)
No difference on that front, yep.
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