A weak memory model. See https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RIS... (by Dan Lustig at Nvidia, NV is both very involved in Arm and RISC-V).
It has a weak memory model by default, but you can opt in to TSO (like x86) as an optional extension.
And for Arm too, you can ship stronger memory models up to SC.
There's also the RCpc extension for memory accesses w/ another memory model there.
Is RCpc still multi-copy atomic? (Which AFAIK is a guaranteed behavior of the Aarch64 memory model)
The RISC-V is presumably very 'greenfield' regarding its memory model, I imagine they've made their decision based on all this knowledge.