13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by GeorgeTirebiter on Saturday November 14, 2020 @04:05PM (#25095608)

Seems to me starting with microprogramming adds complexity that doesn't necessarily make sense for a risc instruction set? Heck, this guy does a Verilog Z-80 without microprogramming. https://dl.acm.org/doi/book/10.5555/3199987

While true the microprogramming ops are much simpler, the inherent parallelism means writing that stuff and getting it correct is usually challenging.

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by musicale on Saturday November 14, 2020 @05:41PM (#25096344)

I think the "microprogramming" bit can/should simply be a multi-cycle, non-pipelined implementation.

Non-pipelined is easier to write and debug, especially if you are used to regular sequential programming; once you have that working then it isn't too hard to turn it into a pipelined implementation.

A basic RISC style design is probably easier than a Z-80 because of the simpler addressing modes and the simpler decode.

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