13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by blkknightarms on Saturday November 14, 2020 @01:41PM (#25094477)

As a computer architecture learning process, I suggest building a microprogrammed, single-cycle processor using digital building blocks without an HDL and without library blocks. Then, refactor it to be pipelined (which demands branch stall logic). Next, add branch prediction. Then, refactor in an HDL. Finally, superscalar, VLIW, and/or unified scheduler.

Choosing MICMAC or MMIX would be good macrolanguage target to start with. Remember, the microprogramming ops can be much simpler and VLIW-style.

The microprogram will be a ROM block that runs the decoding and execution of the actual processor's ISA. It's helpful to write a microprogram assembly language and compiler to make maintenance easier.

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by musicale on Saturday November 14, 2020 @05:36PM (#25096318)

Hey, that sounds.... just like a typical computer architecture course. ;-)

disclosure: I love computer architecture courses, and I highly recommend them.

edit: I also think you can skip the microprogramming, but I think I understand what you are getting at, which is that you do a multi-cycle implementation first and then a pipelined implementation.

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by GeorgeTirebiter on Saturday November 14, 2020 @04:05PM (#25095608)

Seems to me starting with microprogramming adds complexity that doesn't necessarily make sense for a risc instruction set? Heck, this guy does a Verilog Z-80 without microprogramming. https://dl.acm.org/doi/book/10.5555/3199987

While true the microprogramming ops are much simpler, the inherent parallelism means writing that stuff and getting it correct is usually challenging.

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by musicale on Saturday November 14, 2020 @05:41PM (#25096344)

I think the "microprogramming" bit can/should simply be a multi-cycle, non-pipelined implementation.

Non-pipelined is easier to write and debug, especially if you are used to regular sequential programming; once you have that working then it isn't too hard to turn it into a pipelined implementation.

A basic RISC style design is probably easier than a Z-80 because of the simpler addressing modes and the simpler decode.

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by klelatti on Saturday November 14, 2020 @03:03PM (#25095162)

Any recommendations for tools / environment to do this?

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by snvzz on Saturday November 14, 2020 @07:23PM (#25096939)

Anything supported by the open FPGA stack (yosys+nextpnr), which does mean iCE40 or ECP5, currently.

I own/recommend iCESugar, as that's a good iCE40 devboard which is dirt cheap on the official shop in aliexpress[0].

Look at ECP5-based ULX3S[1] if you want to get fancy.

More options at [2].

[0]: https://muselab-tech.aliexpress.com/store/5940159

[1]: https://www.crowdsupply.com/radiona/ulx3s

[2]: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by jacquesm on Saturday November 14, 2020 @03:26PM (#25095347)

Go wild:

https://store.digilentinc.com/fpga-development-boards-kits-f...

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by klelatti on Saturday November 14, 2020 @04:05PM (#25095613)

Thank you!

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Re:13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core by jacquesm on Saturday November 14, 2020 @05:43PM (#25096358)

You're welcome. I have one of those (a bit older though), and every now and then I play around with it for a bit to keep my skills alive, it's super impressive what you can do with hardware this flexible. Get something with as much IO as you can find/afford.

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