An ex-ARM engineer critiques RISC-V

Re:An ex-ARM engineer critiques RISC-V by ansible on Sunday November 01, 2020 @02:56PM (#24962015)

Yes, the old, old way of having a single condition code register or the like (which dates back 40+ years) doesn't work well these days.

I like the Mill CPU approach, where every "register" (it doesn't have named registers actually) has the full set of status bits associated with it, and not just for overflow. Things like "not a result" (NaR), which can represent the result of a failed speculative load for example (because the process doesn't have permission to read from that page, for example).

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Re:An ex-ARM engineer critiques RISC-V by saagarjha on Sunday November 01, 2020 @06:19PM (#24963419)

I thought that compilers couldn't really use this effectively…

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Re:An ex-ARM engineer critiques RISC-V by ansible on Sunday November 01, 2020 @08:38PM (#24964169)

> I thought that compilers couldn't really use this effectively…

The status bits part in general, or the speculative load stuff?

They allegedly have all this working, privately. They haven't released any development tools or such to the public.

I've often toyed with the idea of writing an instruction-level simulator (as opposed to the RTL sim or whatever they have internally). But even sticking to the public information, I'd likely be infringing on their patents.

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