An ex-ARM engineer critiques RISC-V

Re:An ex-ARM engineer critiques RISC-V by wbl on Sunday November 01, 2020 @12:57PM (#24961189)

That's one of the tricks. But it doesn't solve the issue of clobbers, which Intel had to introduce new variants of ADD and MUL to solve. Named predicate registers make it all much easier for everyone.

[ Parent | on HN ]

Re:An ex-ARM engineer critiques RISC-V by CalChris on Sunday November 01, 2020 @02:16PM (#24961740)

Thanks. I knew about condition code renaming from discussion with an Intel compiler engineer. I didn't know about clobbers and I'll read up on that.

[ Parent | on HN ]

Re:An ex-ARM engineer critiques RISC-V by wbl on Sunday November 01, 2020 @03:12PM (#24962100)

https://en.m.wikipedia.org/wiki/Intel_ADX is the solution Intel created.

[ Parent | on HN ]