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A comment on An ex-ARM engineer critiques RISC-V. Parent comment

Re:An ex-ARM engineer critiques RISC-V by pizlonator on Sunday November 01, 2020 @12:46PM (#24961107)
One example of 3 is branching on 32-bit add overflow on a 64-bit cpu where you do a 32-bit add, a 64-bit add, and compare/branch on the result.
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