Re:An ex-ARM engineer critiques RISC-V
by bertr4nd on Sunday November 01, 2020 @11:48AM
(#24960672)
I’d be curious to see the instruction sequences for handling overflow without condition codes. I’m not even sure I see how to do it as efficiently as 3 or 5 instructions :-/
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Re:An ex-ARM engineer critiques RISC-V
by pizlonator on Sunday November 01, 2020 @12:46PM
(#24961107)
One example of 3 is branching on 32-bit add overflow on a 64-bit cpu where you do a 32-bit add, a 64-bit add, and compare/branch on the result.