Yes and no. TSMC's process node gives some hard upper limit to what can be built, but whether you can make your design that compact is an open question.

One consideration is that while we think of each transistor as individual and isolated, in reality they are simply wells of n and p type silicon with some oxides and metal thrown in. Because of this we can get unwanted parasitic components and latches. A BJT transistor for example is just a pattern of three silicon types, so it is somewhat inevitable that these will occur, whether they cause issues, and to what extent depends on the design.

Packing everything as tight as possible gives noise concerns, thermal concerns, signal integrity issues ect.

This is not to devalue the achievement of TSMC, but to state that design work is still a work as well.

[1] https://ieeexplore.ieee.org/document/145696

Ok, but doesn't Apple use EDA tools for that? Or did they develop their own?