Re:AMD Is in Advanced Talks to Buy Xilinx
by tails4e on Saturday October 10, 2020 @06:46AM
(#24738043)
The issue I see is they are slow to compile. I write them daily and it's not that hard to lean when you grok the parallel nature, but generating the HW usually takes at least 10 to 30 mins for a medium sized block, that is a bit of a barrier to entry.
Re:AMD Is in Advanced Talks to Buy Xilinx
by coreblocks on Saturday October 10, 2020 @02:40AM
(#24737080)
As an FPGA dev, I tend to think of HDLs akin to HTML than “code”. It’s just a DSL to describe a graph. Actually pretty similar to how tensorflow is designed.
But yes, a software stack would help.