Line 8 of Table 9 is misleading out of context. If you dig into the report itself, it's calculated based on a hypothetical chip with the same number of transistors for each process (Table 7). For example, the 90nm process is listed as yielding "0.7" chips per wafer, which is obviously nonsensical. Line 8 would be more appropriately described as "cost per 90.7 billion transistors", if I am reading the report right.