Not really. The performance-oriented A series can include -- and will continue to include -- features which improve performance at the expensive of inconsistency, such as branch prediction and speculative execution. The R series values consistent behavior over performance, so it won't have those features.

R82 is in-order, but does provide branch prediction. [1]

[1] https://developer.arm.com/ip-products/processors/cortex-r/co...

Another usage for the MMU would be in a virtualization context. The Hypervisor can configure static address translation tables for each RTOS VM.

The MPU (Memory Protection Unit) in the ARM architecture is like an MVP MMU in that it doesn't have the flexibility of an MMU as the MPU has protection domains (ranges of memory and access semantics bits) and doesn't do address translation like an MMU. It is analogous to mprotect()

I haven't used it, but depending on latency and complexity of updating the MPU config, one could dynamically program it to have an arbitrary levels of protection, think hardware range checks at language level array access.

[1] https://static.docs.arm.com/100699/0100/armv8m_architecture_...

https://man7.org/linux/man-pages/man2/mprotect.2.html