I'm pretty sure that it was expressly chosen because it's reasonably documented unlike most SoC chips. Not that this solves the expense and effort with iterating hardware, of course.
At the point where we got access to documentation and very basic support, around $1M USD was paid (part of which was covering the initial shipments of chips though).
I should check on the pyra and see how that is.
I thought I'd check on the project while writing this (every now and then I come across something that reminds me of it), and I see that the Preorder FAQ for the Pyra looks exactly like the one that was up for the Pandora for (what seemed like) years!
I lost the open pandora, and that was a sad day.
Last time I checked, they hadn't corrected the documentation of their previous line of SoCs (almost 10 years old), despite acknowledging the errors I reported many ears ago. You can either consider that personal support was good, or that, by not correcting stuff they know is false, they don't give a damn about wasting every other user's time (and wasting the support staff time again and again each time a user will ask the same question).
I also remember using a simple piece of software from them (a GUI for pins assignment, which basically consisted of a list of checkboxes, or some kind of simple spreadsheet if you want): that super basic thing leaked several gigabytes of memory per hour, just idling. Well, I couldn't let it on 1 hour, I had to take the habit to stop and restart it after 15-20 minutes...
The app you talk about was probably developed by some summer intern on a tight schedule and never documented, then someone else took over.
They literally don't give a flying fuck about software. One manager I had once was so clueless, he couldn't understand that the GUI of the C# app I made had no code behind it, and kept asking why clicking the buttons isn't doing anything no matter how many times I tried to explain that a GUI can exist without functionality and it's a separate effort to implement that.
Certain apps we were using internally were based on same Java version from 12 years ago since the person who developed it is now a senior line manager and also the sole maintainer.
Then they brought in some Agile/Scrum consultant to increase efficiency and he implemented 45 minute daily stand-ups with 10 people and half of them remote via phone from another country and then he spent most of the day chasing us around the building asking how soon story X will be done. Then they outsourced the whole thing to Poland.
Working in that industry as a SW developer has been a colossal pain and a huge setback for my career I try to slowly erase from my resume.
Silicon, lest anyone think you were working in a different industry.
Sadly he passed away before he had the time to really get it off the ground.
Do you know why? In my eyes that would make them a crazy unattractive supplier.
This isn't the kind of environment you'd find many passionate software engineers because most of them leave for greener pastures unless they really care about the product they're working on, but they're rarely qualified to run developer experience departments.
You spoke of the Basebands...that reminded me that Fabrice Bellard works on the other side of the equation [0]. May be, if we are lucky, he turns his attention to fixing mobile phones [1].
I even found a TI 1080p UV DMD and bought a roll of lithographic film to try to get that feature size limit down. My plan was to expose the litho film instead of the wafer directly and build very precise jigs for the film off of a precision machine base I could get for a few grand, with custom built linear motors to move between steps but I got stuck on the physics and math. It looked like I had a solution using neural networks and a DIY laser interferometer as the feedback loop as a shortcut to learning control theory but then got distracted by more urgent matters... c'est la vie
[1] http://sam.zeloof.xyz/category/semiconductor/
[2] http://sam.zeloof.xyz/garage-electron-microscopy-first-image...
I thought the voiceover video for the SEM lithography experiment worked really well ( https://youtu.be/SB94rQtKlKI ). How does the spot size from the SEM compare to the ~1-um resolution you get from the DMD? I assume you're not actually getting 5 nm out of it...?
Edit: Nowadays I only do electronics for personal projects and since I stick to three fabs (a local one one I've got a relationship with and two Chinese specials), I've just got a few manually created DRC templates per fab, # of layers, and max signal speed with a few templates just for RF that I got from a mentor.
Iterations in electronics are really expensive (my last project cost $30k for 10 assembled prototypes not including of our labor) so most people just copy as much of the manufacturers' reference design as they need. They pour over PCB layout notes and look at how the manufacturer or other customers did and mostly just copy them. Most of my engineering decisions are based on about a dozen black box helper apps that take in my fab's capabilities and signal specs and spit out DRC rules. It gets a little trickier with antenna design but that's often outsourced because you need very specialized facilities for FCC certification anyway.
All in all, it's just like working on a complex distributed system. There are so many things to juggle like R&D budget, per unit COGS and space budget, suppliers and part availability, and supply chain orchestration that it ends up being lots of boring work just to coordinate between all the different experts involved with small bursts of productivity when everyone is properly aligned.