I don't really think that's a thing on Intel? Instructions that are unsupported generally noop or do something slowly. (Or trap.)

I thought the two cores had two different ISAs?

they support different subsets [1] of the same x86-64 ISA, so opcodes won't be reused.

[1] well, I hope the larger cores support a superset of the smaller cores, otherwise it would really be insane.

No idea. I'm just responding on the assumption that it's just two Intel architectures, one with fewer extensions.

Unless one of those things is "trap," that's just a horribly byzantine heterogeneous compute design that no general purpose OS will target.