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Re:Nvidia CEO Introduces Nvidia Ampere Architecture, Nvidia ... by ethbro on Thursday May 14, 2020 @10:50AM (#23180220)
I guess this is fundamentally a homogeneous vs heterogeneous ISA question. I.e. is your ISA intended to operate one chip, or multiple cooperative chips / complexes?
Re:Nvidia CEO Introduces Nvidia Ampere Architecture, Nvidia ... by enos_feedler on Thursday May 14, 2020 @02:10PM (#23183180)
Does it make sense for a hardware ISA to express cooperation between chips? I would think HW ISA is meant to control it's local microarchitecture. I could see a virutal ISA or compiler IR built with a multi chip view.