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A comment on RISC-V OS using Rust: Filesystems. Parent comment

Re:RISC-V OS using Rust: Filesystems by sitkack on Tuesday May 12, 2020 @09:53PM (#23162569)
ESP32-S2 has two ULP co-processors, with one based on RISCV instruction set architecture (ULP-RISCV) and the other on finite state machine (ULP-FSM).

ULP-RISCV has the following features:

    support for IMC instruction set
    thirty-two 32-bit general-purpose registers
    32-bit multiplier and divider
    support for interrupts
    boot by the CPU, its dedicated timer, or RTC GPIO
https://www.espressif.com/sites/default/files/documentation/...
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Re:RISC-V OS using Rust: Filesystems by MrBuddyCasino on Wednesday May 13, 2020 @06:00AM (#23165255)
Interesting, wasn't aware. Is the ULP-FSM the same as the one in the original ESP32? I thought that one was programmable / Turing-complete, so not just a FSM?
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Re:RISC-V OS using Rust: Filesystems by sitkack on Wednesday May 13, 2020 @04:30PM (#23171486)
I have never used the ULP-FSM, the new docs for ESP32-S2 are fascinating. My S2 is on its way, I don't yet have the hardware in hand.
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