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A comment on The DooM-chip: no CPU, no opcodes, no instruction counter. Parent comment

Re:The DooM-chip: no CPU, no opcodes, no instruction counter by monocasa on Saturday May 09, 2020 @01:53PM (#23126841)
The SuperFX doesn't really become the main CPU, and has some practical caveats that keep it from doing so. Part of that is that the thing's instruction memory is only 512 bytes.

There are other accelerator chips that do take a more general approach though, like the SA1.

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Re:The DooM-chip: no CPU, no opcodes, no instruction counter by MrBuddyCasino on Saturday May 09, 2020 @04:26PM (#23128023)
To be fair, the SuperFX was the foundation of an actual honest-to-god 32 bit embedded CPU architecture named ARC (Argonaut RISC Core), produced in the billions, because it was apparently quite efficient.

All the more impressive considering the guys making it had no prior experience in CPU design.

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Re:The DooM-chip: no CPU, no opcodes, no instruction counter by monocasa on Saturday May 09, 2020 @05:42PM (#23128534)
Contrary to popular belief the SuperFX and ARC cores are about as different as can be. RISC back then was a buzzword and applied loose and fast; today we wouldn't call SuperFX a RISC chip if not for the decades of describing it as such. ARC is very much a RISC design though.

Totally agreed on how impressive it was though, despite the differences in nomenclature.

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