IBM doubles its 14nm EDRAM density, adds hundreds of megabytes of cache

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by moring on Monday March 09, 2020 @04:07AM (#22523773)

What is the state of adding higher-level logic to the DRAM chips? E.g. clear a whole DRAM row to 0 (blank memory for new processes). With today's processes, we can probably fit whole simple processor cores there easily.

[ Parent | on HN ]

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by imtringued on Monday March 09, 2020 @07:06AM (#22524428)

This is called PIM (processing in memory) and UPMEM [0] has a working implementation.

[0] https://www.anandtech.com/show/14750/hot-chips-31-analysis-i...

[ Parent | on HN ]

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by baybal2 on Monday March 09, 2020 @04:38AM (#22523901)

Latest DDR standard, and supposedly HBM3 in making support range requests

[ Parent | on HN ]

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by amelius on Monday March 09, 2020 @05:51AM (#22524169)

I guess this would expose new risks of timing side channel attacks, though.

[ Parent | on HN ]

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by baybal2 on Monday March 09, 2020 @09:36AM (#22525207)

Don't run untrusted code

[ Parent | on HN ]